Revolution in Semiconductor Packaging Materials: From Silicon based Constraints to Diversified Breakthroughs

As transistor miniaturization approaches the physical limit, the innovation focus of the semiconductor industry is quietly shifting from the inside of chips to the outside. As the "second battlefield" of chip performance, the field of packaging materials is undergoing a profound transformation from relying on silicon-based materials to reconstructing multi-dimensional material systems. Organic interlayers have broken the long-standing monopoly of silicon interlayers, glass substrates have subverted tradition in a cross-border manner, and composite materials have found a delicate balance between performance and cost. These innovations not only reshape the packaging technology roadmap, but also redefine the physical form of chips.
Taking the silicon intermediate layer as an example, it used to be the core of 2.5D packaging, utilizing through silicon via (TSV) technology to achieve interconnection between chips. However, as the integration density of AI chips exceeds 10000 I/O/mm ², the two major defects of the silicon intermediate layer become increasingly prominent. Firstly, there is a serious issue of thermal mismatch. The coefficient of thermal expansion (CTE) of silicon is 2.6 ppm/℃, which is significantly different from the 15-20 ppm/℃ of organic substrates. This results in a 12 inch wafer edge warping of up to 50 μ m, which has a significant negative impact on signal integrity. Secondly, the cost is high. The TSV process requires more than 10 complex processes, and the cost of a single crystal circle exceeds $20000. When the number of stacked layers of chips exceeds 10, the packaging cost exceeds 40%, becoming a huge obstacle to large-scale applications. The stacking of 6 GPU chips in Nvidia H100 has almost reached the engineering limit of silicon interlayer, and material substitution is urgent.
Organic intermediate layers, represented by TSMC CoWoS-R technology, are achieving breakthroughs in silicon-based materials through the use of ABF thin film materials. The CTE of ABF film is matched with the substrate (12ppm/℃), reducing the package warpage rate to 32 μ m (a decrease of 60%). Its dielectric constant is 3.5 (only 1/3 of silicon), reducing signal loss by 40% at 28GHz frequency, which can well meet the requirements of HBM high-speed interconnection. Moreover, this technology does not require TSV process and directly constructs an interconnect network through a 2 μ m line width redistribution layer (RDL), reducing the cost of single crystal circles by 40% and promoting the penetration rate of CoWoS technology in chips below 7nm by over 60%. Samsung has further increased the number of ABF thin film RDL layers from 8 to 12, which can interconnect 2000 chips in a 15mm × 15mm package. The integration density is three times higher than that of silicon interlayers, making it a key factor in the economic integration of Chiplets.
In 2025, BOE began production of glass substrate test lines, marking a comeback of display materials in the semiconductor field. The dielectric constant of this glass substrate material is 4.0 tanδ = 0.002， The loss in the 60GHz millimeter wave frequency band is reduced by 50%, the flatness error is less than 1 μ m, and it supports a line width of 1.5 μ m (while the silicon wafer limit is 3 μ m), making it an ideal carrier for 5G chips. At the same time, it can withstand high temperatures of 400 ℃ and support ultra large size packaging of 120mm × 120mm (the silicon interlayer is only 80mm × 80mm). With the help of this glass substrate, Nuoshi Technology has achieved a hot spot temperature of ≤ 85 ℃ and a 3-fold increase in thermal management efficiency for Micro LED chips at a brightness of 500000 nits. Intel has increased the density of glass via holes (TGVs) to 5 times that of TSV (100000 per cm ²) through laser modification technology, and achieved a copper filling yield of 95%, laying the foundation for HBM4's 1024 bit wide interface.
However, a single material often struggles to meet complex and ever-changing demands, and hybrid integration is becoming a new development direction, such as "organic silicon" synergy. The composite adapter board of Yuntian Semiconductor has a bottom layer ABF film for absorbing thermal stress, and an upper layer silicon bridge for transmitting high-frequency signals, achieving a line width of 1.5 μ m on an area of 2700mm ². Through actual testing, the reliability of the 12nm AI chip has been improved by 25%. Xinyue Chemical's low dielectric glass paste (DK=3.2) has reduced RDL costs by 30% and achieved a yield rate of 98% through screen printing instead of sputtering, greatly enhancing the cost-effectiveness of small and medium-sized chip packaging. These material combinations not only retain the high-frequency advantage of silicon, but also solve the problems of thermal matching and cost through organic/glass layers, becoming the core element of differentiated competition for enterprises.
Of course, the material revolution cannot be separated from the synergy of the entire industry chain. On the device side, ASML High NA EUV has added a glass substrate exposure mode, reducing mask usage by 40% and shortening single crystal circle exposure time to 20 minutes. In terms of process, Lam Research optimized the PECVD gas formula, which increased the deposition rate of the glass substrate insulation layer by 50% and reduced the defect density to 0.1/cm ². In terms of standard setting, TSMC promotes the standardization of organic/glass substrate interfaces and supports 0.8 μ m copper glass bonding; The "Chip to Chip Interconnection Protocol 2.0" released by China defines the signal integrity specification for glass substrates, which helps to build a domestic ecosystem.
It should be noted that although the prospects are very bright, there are still some bottlenecks. For example, glass substrates have brittleness issues, and the cutting yield of 120mm × 120mm specifications is only 65%. However, Corning is developing zirconium doped glass with the goal of increasing fracture toughness to 1.2 MPa · m ¹/², close to the level of silicon wafers. Meanwhile, in terms of the temperature resistance of organic materials, taking ABF thin films as an example, they decompose at 260 ℃, which limits their application in the field of power chips. But Dow Chemical's polyimide modified material has reached a temperature resistance of 350 ℃ and is expected to achieve mass production by 2026. In addition, in terms of the reliability of composite interfaces, the delamination rate of the "organic silicon" interface can reach 18% within 1000 hours in humid and hot environments. IMEC is developing nanocrystalline bonding technology to improve stability.